• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with extensive low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 5 µs.

The MSP430F5329, MSP430F5327, and MSP430F5325 are microcontroller configurations with an integrated 3.3-V LDO, four 16-bit timers, a high-performance 12-bit analog-to-digital converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities, and 63 I/O pins.

特性

• Low Supply-Voltage Range: 1.8 V to 3.6 V
• Ultralow Power Consumption
  • Active Mode (AM):
    All System Clocks Active
    290 µA/MHz at 8 MHz, 3.0 V, Flash Program Execution (Typical)
    150 µA/MHz at 8 MHz, 3.0 V, RAM Program Execution (Typical)
  • Standby Mode (LPM3):
    Real Time Clock With Crystal , Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wake-Up:
    1.9 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)
    Low-Power Oscillator (VLO), General Purpose Counter, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wake-Up:
    1.4 µA at 3.0 V (Typical)
  • Off Mode (LPM4):
    Full RAM Retention, Supply Supervisor Operational, Fast Wake-Up:
    1.1 µA at 3.0 V (Typical)
  • Shutdown Mode (LPM4.5):
    0.18 µA at 3.0 V (Typical)
• Wake-Up From Standby Mode in Less Than 5 µs
• 16-Bit RISC Architecture, Extended Memory, Up to 25-MHz System Clock
• Flexible Power Management System
  • Fully Integrated LDO With Programmable Regulated Core Supply Voltage
  • Supply Voltage Supervision, Monitoring, and Brownout
• Unified Clock System
  • FLL Control Loop for Frequency Stabilization
  • Low-Power/Low-Frequency Internal Clock Source (VLO)
  • Low-Frequency Trimmed Internal Reference Source (REFO)
  • 32-kHz Watch Crystals (XT1)
  • High-Frequency Crystals Up to 32 MHz (XT2)
• 16-Bit Timer TA0, Timer_A With Five Capture/Compare Registers
• 16-Bit Timer TA1, Timer_A With Three Capture/Compare Registers
• 16-Bit Timer TA2, Timer_A With Three Capture/Compare Registers