IS65WV25616DBLL
FEATURES
• High-speed access time: 35, 45, 55 ns
• CMOS low power operation
30 mW (typical) operating
6 μW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
1.65V--2.2V Vdd (IS62WV25616DALL)
2.5V--3.6V Vdd (IS62/65WV25616DBLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperature support
• Lead-free available
• 2 CS option available
DESCRIPTION
The ISSI IS62WV25616DALL and IS62/65WV25616DBLL
are high-speed, low power, 4M bit SRAMs organized as
256K words by 16 bits. It is fabricated using ISSI's highperformance
CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is low
(deselcted) or when CS1 is LOW, CS2 is HIGH and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable (WE)
controls both writing and reading of the memory. A data byte
allows Upper Byte (UB) and Lower Byte (LB) access.
The IS62WV25616DALL and IS62/65WV25616DBLL are
packaged in the JEDEC standard 44-Pin TSOP (TYPE II)
and 48-pin mini BGA (6mmx8mm).
