IS61LF6432A
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP package
• Power Supply:
+3.3V VDD
+3.3V or 2.5V VDDQ
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
• Industrial Temperature Available:
(-40oC to +85oC)
• Lead-free available
DESCRIPTION
The ISSI IS61LF6432A and IS61LF6436A are high-speed,
low-power synchronous static RAM designed to provide a
burstable, high-performance, memory. IS61LF6432A is
organized as 65,536 words by 32 bits. IS61LF6436A is
organized as 65,536 words by 36 bits. They are fabricated
with ISSI's advanced CMOS technology. The device integrates
a 2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BWa controls DQa, BWb controls DQb, BWc controls DQc,
BWd controls DQd, conditioned by BWE being LOW. A
LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61LF6432A/36A and controlled by the
ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left
floating.
