CYDC128B16-55AXI
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ 4/8/16 K × 16 and 8/16 K × 8 organization
■ High speed access: 40 ns
■ Ultra low operating power
❐ Active: ICC = 15 mA (typical) at 55 ns
❐ Active: ICC = 25 mA (typical) at 40 ns
❐ Standby: ISB3 = 2 μA (typical)
■ Port-independent 1.8 V, 2.5 V, and 3.0 V I/Os
■ Pb-free 14 × 14 × 1.4 mm 100-pin Thin Quad Flat Pack (TQFP)
Package
■ Full asynchronous operation
■ Pin select for master or slave
■ Expandable data bus to 32 bits with master/slave chip select
when using more than one device
■ On-chip arbitration logic
■ On-chip semaphore logic
■ Input read registers (IRR) and output drive registers (ODR)
■ INT flag for port-to-port communication
■ Separate upper byte and lower byte control
■ Commercial and industrial temperature ranges
