CY7C1163KV18-400BZI
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 550-MHz clock for high bandwidth
■ Four-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR® II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to QDR I device with one cycle read latency
when DOFF is asserted LOW
■ Available in x18, and x36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V± 0.1 V; I/O VDDQ = 1.4 V to VDD
[1]
❐ Supports both 1.5 V and 1.8 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm
Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase-locked loop (PLL) for accurate data placement
