CY7C006A-20AXI
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ 16 K × 8 organization (CY7C006A)
■ 0.35-micron CMOS for optimum speed/power
■ High-speed access: 20 ns
■ Low operating power
❐ Active: ICC = 180 mA (typical)
❐ Standby: ISB3 = 0.05 mA (typical)
■ Fully asynchronous operation
■ Automatic power-down
■ Expandable data bus to 16 bits or more using
Master/Slave chip select when using more than one
device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flags for port-to-port communication
■ Pin select for Master or Slave
■ Commercial temperature range
■ Available in 68-pin PLCC (CY7C006A), 64-pin TQFP
(CY7C006A)
■ Pb-free packages available
I/O
Control
Address
Decode
A0L–A13L
CEL
OEL
R/WL
BUSYL
I/O
Control
Interrupt
Semaphore
Arbitration
SEML
INTL
