• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT825T is an 8-bit buffered register with all the CY74FCT823T controls, plus multiple enables (OE\₁, OE\₂, OE\₃) to allow multiuser control of the interface, e.g., CS\, DMA, and RD/WR\. This device is ideal for use as an output port requiring high I_OL/I_OH.

This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.

This device is fully specified for partial-power-down applications using I_off.

特性

• Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29825
• Reduced V_OH (Typically = 3.3 V) Version of Equivalent FCT Functions
• Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
• I_off Supports Partial-Power-Down Mode Operation
• Matched Rise and Fall Times
• Fully Compatible With TTL Input and Output Logic Levels
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• 64-mA Output Sink Current
  32-mA Output Source Current
• High-Speed Parallel Register With Positive-Edge-Triggered D-Type Flip-Flops
• Buffered Common Clock-Enable (EN\) and Asynchronous-Clear (CLR\) Inputs
• 3-State Outputs