• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The CY74FCT2646T consists of a bus transceiver circuit with 3-state, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers as the appropriate clock pin goes to a high logic level. Output-enable (G\) and direction-control (DIR) inputs determine the transceiver function. On-chip termination resistors at the outputs reduce system noise caused by reflections, so that the CY74FCT2646T can replace the CY74FCT646T in an existing design.

In the transceiver mode, data present at the high-impedance port can be stored in either the A or B register, or in both. Select controls (SAB, SBA) can multiplex stored and real-time (transparent mode) data.

特性

• Function and Pinout Compatible With FCT and F Logic
• Reduced V_OH (Typically = 3.3 V) Versions of Equivalent FCT Functions
• 25- Output Series Resistors to Reduce Transmission-Line Reflection Noise
• Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
• I_off Supports Partial-Power-Down Mode Operation
• Matched Rise and Fall Times
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• Fully Compatible With TTL Input and Output Logic Levels
• 12-mA Output Sink Current
  15-mA Output Source Current
• Independent Register for A and B Buses
• 3-State Outputs