• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I₀, I₁ as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S₀ and S₁).

The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.

特性

• Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29520
• Reduced V_OH (Typically = 3.3 V) Version of Equivalent FCT Functions
• Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
• I_off Supports Partial-Power-Down Mode Operation
• Matched Rise and Fall Times
• Fully Compatible With TTL Input and Output Logic Levels
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• Single- and Dual-Pipeline Operation Modes
• Multiplexed Data Inputs and Outputs
• CY29FCT520T
  • 64-mA Output Sink Current
    32-mA Output Source Current
• CY29FCT520ATDMB, CY29FCT520BTDMB
  • 32-mA Output Sink Current
    12-mA Output Source Current
• 3-State Outputs