• Qualified for Automotive Applications
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Positive Edge Clocking
• Typical f_MAX = 60 MHz at V_CC = 5 V,
  C_L = 15 pF, T_A = 25°C
• Fanout (Over Temperature Range)
  • Standard Outputs . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . 15 LSTTL Loads
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• V_CC Voltage = 2 V to 6 V
• High Noise Immunity N_IL or N_IH = 30% of V_CC, V_CC = 5 V

DESCRIPTION/ORDERING INFORMATION

The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low, and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low