• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

CD4031B is a static shift register that contains 64 D-type, master-slave flip-flop stages and one stage which is a D-type master flip-flop only (referred to as a 1/2 stage).

The logic level present at the DATA input is transferred into the first stage and shifted one stage at each positive-going clock transition. Maximum clock frequencies up to 12 Megahertz (typical) can be obtained. Because fully static operation is allowed, information can be permanently stored with the clock line in either the low or high state. The CD4031B has a MODE CONTROL input that, when in the high state, allows operation in the recirculating mode. The MODE CONTROL input can also be used to select between two separate data sources. Register packages can be cascaded and the clock lines driven directly for high-speed operation.

特性

• Fully static operation: DC to 12 MHz typ. @ V_DD - V_SS = 15 V
• Standard TTL drive capability on Q output
• Recirculation capability
• Three cascading modes:
  • Direct clocking for high-speed operation
  • Delayed clocking for reduced clock drive requirements
  • Additional 1/2 stage for slow clocks
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100nA at 18 V and 25°C
• Noise margin (over full package-temperature range):
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
     2.5 V at V_DD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"
• Applications:
  • Serial shift register
  • Time delay circuits