品牌索引
产品分类 > 小信号开关二极管> 瞬态电压抑制器TVS/ESD> 双极管二极管> 调谐二极管> 齐纳(稳压)二极管> 小信号肖特基二极管> 频带转换二极管> 中/高功率管> 射频PIN二极管> Sinterglass二极管> 整流器 > N沟道(N-Channel)> P沟道(P-Channel)> 双N沟道(Dual N-Channel)> 双P沟道(Dual P-Channel)> 双N和P沟道(Dual N and P-Channel)
|
产品介绍
Ultralow power, high performance transceiver Frequency bands: 902 MHz to 958 MHz Data rates supported: 1 kbps to 300 kbps 2.2 V to 3.6 V power supply Single-ended and differential power amplifiers (PAs) Low IF receiver with programmable IF bandwidths 100 kHz, 150 kHz, 200 kHz, 300 kHz Receiver sensitivity (BER) −116 dBm at 1.0 kbps, 2FSK, GFSK −107.5 dBm at 38.4 kbps, 2FSK, GFSK −106.5 dBm at 50 kbps, 2FSK, GFSK −105 dBm at 100 kbps, 2FSK, GFSK −104 dBm at 150 kbps, GFSK, GMSK −103 dBm at 200 kbps, GFSK, GMSK −100.5 dBm at 300 kbps, GFSK, GMSK Very low power consumption 12.8 mA in PHY_RX mode (maximum front-end gain) 11.9 mA in PHY_RX mode (AGC off, ADC off) 24.1 mA in PHY_TX mode (10 dBm output, single-ended PA) 0.75 μA in PHY_SLEEP mode (32 kHz RC oscillator active) 1.28 μA in PHY_SLEEP mode (32 kHz XTAL oscillator active) 0.33 μA in PHY_SLEEP mode (Deep Sleep Mode 1) RF output power of −20 dBm to +13.5 dBm (single-ended PA) RF output power of −20 dBm to +10 dBm (differential PA) Patented fast settling automatic frequency control (AFC) Digital received signal strength indication (RSSI) Integrated PLL loop filter and Tx/Rx switch Fast automatic voltage controlled oscillator (VCO) calibration Automatic synthesizer bandwidth optimization On-chip, low power, custom 8-bit processor Radio control Packet management Smart wake mode SPORT mode support High speed synchronous serial interface to Tx and Rx Data for direct interfacing to processors and DSPs Packet management support Highly flexible for a wide range of packet formats Insertion/detection of preamble/sync word/CRC/address Manchester and 8b/10b data encoding and decoding Data whitening Smart wake mode Current saving low power mode with autonomous receiver wake up, carrier sense, and packet reception Downloadable firmware modules Image rejection calibration, fully automated (patent pending) 128-bit AES encryption/decryption with hardware acceleration and key sizes of 128 bits, 192 bits, and 256 bits Reed-Solomon error correction with hardware acceleration 240-byte packet buffer for Tx/Rx data Efficient SPI control interface with block read/write access Integrated battery alarm and temperature sensor Integrated RC and 32.768 kHz crystal oscillator On-chip, 8-bit ADC 5 mm × 5 mm, 32-lead, LFCSP package |
