73S1209F TEATURES
80515 Core:
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1 clock cycle per instruction (most instructions)
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CPU clocked up to 24MHz
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32kB Flash memory with security
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2kB XRAM (User Data Memory)
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256 byte IRAM
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Hardware watchdog timer
Oscillators:
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Single low-cost 6MHz to 12MHz crystal
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An Internal PLL provides all the necessary clocks to each block of the system
Interrupts:
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Standard 80C515 4-priority level structure
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9 different sources of interrupt to the core
Power Down Modes:
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2 standard 80C515 Power Down and IDLE modes
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Extensive device power down mode
Timers:
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(2) Standard 80C52 timers T0 and T1
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(1) 16-bit timer
Built-in ISO-7816 Card Interface:
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Linear regulator produces VCC for the card (1.8V, 3V or 5V)
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Full compliance with EMV 4.1
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Activation/Deactivation sequencers
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Auxiliary I/O lines (C4 and C8 signals)
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7kV ESD protection on all interface pins
Communication with Smart Cards:
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ISO-7816 UART for protocols T=0, T=1
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(2) 2-Byte FIFOs for transmit and receive
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Configured to drive multiple external Teridian 73S8010x interfaces (for multi-SAM architectures)
